The present invention relates to a method and an apparatus for inspecting defects. More specifically, the present invention relates to a method and an apparatus for inspecting defects that measure, at high speed and precision, surfaces of a semiconductor wafer etc. on which many IC chips containing semiconductor circuits therein are formed.
Optical apparatuses are mainly used for inspecting defects of circuit patterns on semiconductor wafers. One such apparatus sequentially picks up images of circuit patterns inside an LSI chip with an image pick-up sensor by scanning a stage on which a wafer is mounted. A circuit-pattern image is compared with a circuit-pattern image of an adjacent chip stored temporarily, and a defect is detected by extracting a difference by image processing. Extraction of the difference depends on scanning accuracy of the stage, and there exists a problem of a shift in position occurring between images of neighboring chips. In order to correct the positional shift of images with one picture element pitch or less of accuracy of the image pick-up sensor, JP-A-9-128540 discloses a method, for example, in which a luminance value at a shift position being one picture-element pitch or less is calculated from luminance values of four spots of neighboring picture elements by inner interpolation.
Also, JP-A-9-264728 discloses a method for calculating a size of a defect from a group of picture elements of an extracted difference. Further, JP-A-2005-294521 discloses a method in which classification of defects such as foreign objects on a rear surface, unevenness, etc. is performed from a direction of a luminance gradient of the extracted group of picture elements.
Still further, JP-T-2005-520123 discloses a method in which picture elements in the stage scanning direction are added and a noise of the image is reduced by combining stage scanning with a two-dimensional CMOS sensor and, also, a method in which a color (RGB) image is picked up by using a color strobe light or a color filter.
On the other hand, as an exposure technology for a printed circuit board, JP-A-2003-84444 discloses a method in which a circuit pattern is directly drawn on a substrate without using a mask for projection but by scanning a stage on which the substrate is mounted and with the use of a micro-mirror array element. In this method, by inclining the stage scanning direction and the direction of the micro-mirror array element by a predetermined angle, a drawing position is controlled with an array-element pitch or less of accuracy.
Still further, JP-A-9-210917 discloses a technology in which a noise of scattered light entering a linear sensor from a circuit pattern on a wafer is reduced by inclining a direction of the wafer at a predetermined angle to the linear sensor and the stage-scanning direction.
As described above, position correction of the image takes time because interpolation calculation of luminance values is necessary from the neighboring picture elements. Further, since linear interpolation is adopted, when the size of the picture element is large with respect to non-linear luminance change, the interpolated luminance value has an error with respect to a luminance value of an actual sample. In this regard, in extracting a defect based on a difference from an adjacent image, there may take place false detection or failing in detecting the defect. On the other hand, also in calculating a size of a defect and classifying defects, calculation can only be carried out by sampling points determined by a size of the picture element with respect to an actual size or shape. Therefore, there is a limit for accuracy in the size and classification.
These problems can be solved by reducing the picture element in size and increasing magnifying power for image pick-up to reduce an area to be inspected on a sample. However, since an image pick-up field becomes smaller, when inspecting a wafer or an entire substrate, the number of reciprocating motions of the stage increases, lowering an inspection throughput.